The present invention relates generally to integrated circuit (IC) designs, and more particularly to an electrostatic discharge (ESD) protection system for multiple-domain ICs.
A gate oxide of a metal-oxide-semiconductor (MOS) transistor of an IC is very susceptible to damage. The gate oxide may be destroyed by being contacted with a voltage only a few volts higher than a supply voltage of the IC. It is understood that a regular supply voltage is 5.0, 3.3 volts or even lower. Electrostatic voltages from common environmental sources can easily reach thousands, or even tens of thousands of volts. Such voltages are destructive even though the charge and any resulting current are small. For this reason, it is of critical importance to provide the IC with an ESD protection circuit.
An ESD can occur in many forms, for example, when a person touches some of the pads on the IC. This is the same static electricity that may be painfully experienced by a person who walks across a carpet on a dry day and then touches a grounded metal object. When an ESD event occurs, the ESD protection circuit must quickly become conductive so that the electrostatic charge is conducted to ground and is dissipated before it can damage core circuitry of the IC.
An IC may include one or more circuit domains, such as a digital domain and an analog domain. Conventionally, a grounded-gate NMOS (GGNMOS) transistor is implemented in the multiple-domain IC for dissipating the ESD current to ground through an I/O ground rail during a cross-domain ESD event. However, before the GGNMOS transistor can pass the ESD current to the I/O ground rail, the current may find an unexpected path across the multiple domains to ground. As a result, the electronic components disposed along the unexpected path may be damaged by the ESD current. This unexpected damage can occur more frequently as the semiconductor technology advances to nanometer scales.
thus it is desirable to have an ESD protection system that can avoid the ESD current being dissipated through an unexpected path during a cross-domain ESD event.